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| Freescale Semiconductor Advance Information Document Number: 33937 Rev. 5.0, 4/2009 Three Phase Field Effect Transistor Pre-driver The 33937 and 33937A are Field Effect Transistor (FET) predrivers designed for three phase motor control and similar applications. The 33937A has been specifically enhanced to improve performance when driving very high current loads. The integrated circuit (IC) uses SMARTMOSTM technology. The IC contains three High Side FET pre-drivers and three Low Side FET pre-drivers.Three external bootstrap capacitors provide gate charge to the High Side FETs. The IC interfaces to a MCU via six direct input control signals, an SPI port for device setup and asynchronous reset, enable and interrupt signals. Both 5.0 and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are provided. Features * Fully specified from 8.0 to 40 V covers 12 and 24 V automotive systems * Extended operating range from 6.0 to 58 V covers 12 and 42 V systems * Greater than 1.0 A gate drive capability with protection * Protection against reverse charge injection from CGD and CGS of external FETs * Includes a charge pump to support full FET drive at low battery voltages * Deadtime is programmable via the SPI port * Simultaneous output capability enabled via safe SPI command * Pb-free packaging designated by suffix code EK VSYS VPUMP PUMP VPWR VLS VDD VSS 3 3 3 33937 THREE-PHASE PRE-DRIVER EK SUFFIX (Pb-FREE) 98ASA99334D 54-PIN SOICW-EP ORDERING INFORMATION Device MCZ33937EK/R2 PCZ33937AEK/R2 Temperature Range (TA) -40C to 135C Package 54 SOICW-EP 33937 VSUP PA_HS_G PB_HS_G PC_HS_G PA_HS_S PB_HS_S PC_HS_S MCU OR DSP PX_HS PX_LS PHASEX CS SI SCLK SO RST INT EN1 GND EN2 PA_LS_G PB_LS_G PC_LS_G PX_LS_S AMP_P AMP_N AMP_OUT RSEN Figure 1. 33937 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2008-2009. All rights reserved. INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM PUMP VPWR VSUP VPUMP PGND MAIN CHARGE PUMP TRICKLE CHARGE PUMP 5.0 V REG. VDD OSCILLATOR UV DETECT 3X HOLD -OFF CIRCUIT VLS REG. VLS VDD RST INT EN1 EN2 PX_HS PX_LS CS SI SCLK SO PHASEX OC_OUT GND(2) + OVER-CUR. COMP. 3 3 3 T-LIM VSUP + DESAT. 1.4 V COMP + HIGH SIDE DRIVER PX_BOOT PX_HS_G CONTROL LOGIC PX_HS_S + PHASE VSUP COMP. LOW SIDE DRIVER PX_LS_G + I-SENSE AMP. AMP_N AMP_P VLS_CAP PX_LS_S VSS OC_TH AMP_OUT Figure 2. 33937 Simplified Internal Block Diagram 33937 2 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS PIN CONNECTIONS PHASEA PGND EN1 EN2 RST N/C PUMP VPUMP VSUP PHASEB PHASEC PA_HS PA_LS VDD PB_HS PB_LS INT CS SI SCLK SO PC_LS PC_HS AMP_OUT AMP_N AMP_P OC_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 .35 34 33 32 31 30 29 28 Transparent Top View VPWR N/C N/C VLS N/C N/C PA_BOOT PA_HS_G PA_HS_S PA_LS_G PA_LS_S PB_BOOT PB_HS_G PB_HS_S PB_LS_G PB_LS_S PC_BOOT PC_HS_G PC_HS_S PC_LS_G PC_LS_S N/C VLS_CAP GND1 GND0 VSS OC_TH Figure 3. 33937 Pin Connections Table 1. 33937 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 22. Pin 1 2 3 4 5 6, 33, 49, 50, 52, 53 7 8 9 10 11 Pin Name PHASEA PGND EN1 EN2 RST N/C PUMP VPUMP VSUP PHASEB PHASEC Pin Function Digital Output Ground Digital Input Digital Input Digital Input - Power Drive Out Power Input Analog Input Digital Output Digital Output Formal Name Phase A Power Ground Enable 1 Enable 2 Reset No Connect Pump Voltage Pump Supply Voltage Phase B Phase C Definition Totem Pole output of Phase A comparator. This output is low when the voltage on PA_HS_S (Source of High Side FET) is less than 50% of VSUP Power ground for charge pump Logic signal input must be high (ANDed with EN2) to enable any gate drive output. Logic signal input must be high (ANDed with EN1) to enable any gate drive output Reset input Do not connect these pins Charge pump output Charge pump supply Supply voltage to the load. This pin is to be connected to the common Drains of the external High Side FETs Totem Pole output of Phase B comparator. This output is low when the voltage on PB_HS_S (Source of High Side FET) is less than 50% of VSUP Totem Pole output of Phase C comparator. This output is low when the voltage on PC_HS_S (Source of High Side FET) is less than 50% of VSUP 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS Table 1. 33937 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 22. Pin 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30, 31 32 34 35 36 37 38 39 40 41 42 43 44 Pin Name PA_HS PA_LS VDD PB_HS PB_LS INT CS SI SCLK SO PC_LS PC_HS AMP_OUT AMP_N AMP_P OC_OUT OC_TH VSS GND VLS_CAP PC_LS_S PC_LS_G PC_HS_S PC_HS_G PC_BOOT PB_LS_S PB_LS_G PB_HS_S PB_HS_G PB_BOOT PA_LS_S Pin Function Digital Input Digital Input Analog Output Digital Input Digital Input Digital Output Digital Input Digital Input Digital Input Digital Output Digital Input Digital Input Analog Output Analog Input Analog Input Digital Output Formal Name Phase A High Side Phase A Low Side VDD Regulator Phase B High Side Phase B Low Side Interrupt Chip Select Serial In Serial Clock Serial Out Phase C Low Side Phase C High Side Amplifier Output Amplifier Invert Amplifier Non-Invert Over-current Out Definition Active low input logic signal enables the High Side Driver for Phase A Active high input logic signal enables the Low Side Driver for Phase A VDD regulator output capacitor connection. Active low input logic signal enables the High Side Driver for Phase B Active high input logic signal enables the Low Side Driver for Phase B Interrupt pin output Chip Select input. It frames SPI commands and enables SPI port Input data for SPI port. Clocked on the falling edge of SCLK, MSB first Clock for SPI port and typically is 3.0 MHz Output data for SPI port. Tri-state until CS becomes low Active high input logic signal enables the Low Side Driver for Phase C Active low input logic signal enables the High Side Driver for Phase C Output of the current-sensing amplifier Inverting input of the current-sensing amplifier Non-inverting input of the current-sensing amplifier Totem pole digital output of the Over-current Comparator Analog Input Over-current Threshold Threshold of the over-current detector Ground Ground Voltage Source Supply Ground reference for logic interface and power supplies Ground Substrate and ESD reference, connect to VSS VLS Regulator connection for additional output capacitor, providing low impedance supply source for Low Side Gate Drive Source connection for Phase C Low Side FET Analog Output VLS Regulator Output Capacitor Power Input Phase C Low Side Source Power Output Phase C Low Side Gate Gate drive output for Phase C Low Side Drive Power Input Power Output Analog Input Power Input Phase C High Side Source Phase C High Side Gate Drive Phase C Bootstrap Phase B Low Side Source Source connection for Phase C High Side FET Gate Drive for output Phase C High Side FET Bootstrap capacitor for Phase C Source connection for Phase B Low Side FET Power Output Phase B Low Side Gate Gate Drive for output Phase B Low Side Drive Power Input Power Output Analog Input Power Input Phase B High Side Source Phase B High Side Gate Drive Phase B Bootstrap Phase A Low Side Source Source connection for Phase B High Side FET Gate Drive for output Phase B High Side Bootstrap capacitor for Phase B Source connection for Phase A Low Side FET 33937 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 1. 33937 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 22. Pin 45 46 47 48 51 54 Pin Name PA_LS_G PA_HS_S PA_HS_G PA_BOOT VLS VPWR EP Pin Function Formal Name Definition Power Output Phase A Low Side Gate Gate Drive for output Phase A Low Side Drive Power Input Power Output Analog Input Analog Output Power Input Ground Phase A High Side Source Phase A High Side Gate Drive Phase A Bootstrap VLS Regulator Voltage Power Exposed Pad Source connection for Phase A High Side FET Gate Drive for output Phase A High Side Bootstrap capacitor for Phase A VLS regulator output. Power supply for the gate drives Power supply input for gate drives Device will perform as specified with the Exposed Pad un-terminated (floating) however, it is recommended that the Exposed Pad be terminated to pin 29 (VSS) and system ground 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 5 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings All voltages are with respect to VSS unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ELECTRICAL RATINGS VSUP Supply Voltage Normal Operation (Steady-state) Transient Survival(1) VPWR Supply Voltage Normal Operation (Steady-state) Transient Survival(1) Charge Pump (PUMP, VPUMP) VLS Regulator Outputs (VLS, VLS_CAP)(2) Logic Supply Voltage Logic Output (INT, SO, PHASEA, PHASEB, PHASEC, OC_OUT)(3) Logic Input Pin Voltage (EN1, EN2, Px_HS, Px_LS, SI, SCLK, CS, RST) 10 mA Amplifier Input Voltage (Both Inputs-GND), (AMP_P - GND) or (AMP_N - GND) 6.0 mA source or sink Over-current comparator threshold 10 mA Driver Output Voltage (4) Symbol Value Unit VSUP 58 -1.5 to 80 VPWR 58 -1.5 to 80 VPUMP VLS VDD VOUT VIN VIN_A -7.0 to 7.0 VOC VBOOT VHS_G VLS_G VHS_G VHS_S VLS_G VLS_S -0.3 to 7.0 75 75 16 -0.3 to 40 -0.3 to 18 -0.3 to 7.0 -0.3 to 7.0 -0.3 to 7.0 V V V V V V V V V V High Side bootstrap (PA_BOOT, PB_BOOT, PC_BOOT) High Side (PA_HS_G, PB_HS_G, PC_HS_G) Low Side (PA_LS_G, PB_LS_G, PC_LS_G) Driver Voltage Transient Survival (5) V -7.0 to 75.0 -7.0 to 75.0 -7.0 to 18.0 -7.0 to 7.0 High Side (PA_HS_G, PB_HS_G, PC_HS_G, PA_HS_S, PB_HS_S, PC_HS_S) Low Side (PA_LS_G, PB_LS_G, PC_LS_G, PA_LS_S, PB_LS_S, PC_LS_S) Notes 1. The device will withstand load dump transient as defined by ISO7637 with peak voltage of 80 V. 2. Normal operation of the 33937 at VPWR voltages greater than 28V can result in degradation or failure of the VLS regulator due to transients induced during a RESET. A 20 V transient suppressor is recommended on the VLS pin (pin 51) to prevent excessive stress under these conditions. Using the 33937A will avoid this limitation. 3. Short-circuit proof, the device will not be damaged or induce unexpected behavior due to shorts to external sources within this range. 4. This voltage should not be applied without also taking voltage at HS_S and voltage at PX_LS_S into account. 5. Actual operational limitations may differ from survivability limits. The VLS - VLS_S differential and the VBOOT - VHS_S differential must be greater than 3.0 V to insure the output gate drive will maintain a commanded OFF condition on the output. 33937 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 2. Maximum Ratings (continued) All voltages are with respect to VSS unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ESD Voltage(6) Human Body Model - HBM (All pins except for the pins listed below) Pins: PA_Boot, PA_HS_S, PA_HS_G, PB_Boot, PB_HS_S, PB_HS_G, PC_Boot, PC_HS_S, PC_HS_G, VPWR Charge Device Model - CDM Corner pins All other pins THERMAL RATINGS Storage Temperature Operating Junction Temperature Thermal Resistance (7) Symbol VESD Value Unit V 2000 1000 750 300 TSTG TJ RJC TSOLDER -55 to +150 -40 to +150 C C C/W Junction-to-Case Soldering Temperature(8) 3.0 Note 9 C Notes 6. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ) and the Charge Device Model (CDM), Robotic (CZAP = 4.0 pF). 7. Case is considered EP - pin 55 under the body of the device. The actual power dissipation of the device is dependent on the operating mode, the heat transfer characteristics of the board and layout and the operating voltage. See Figure 24 and Figure 25 for examples of power dissipation profiles of two common configurations. Operation above the maximum operating junction temperature will result in a reduction in reliability leading to malfunction or permanent damage to the device. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. 8. 9. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic POWER INPUTS VPWR Supply Voltage Startup Threshold(10) VSUP Supply Current, VPWR = VSUP = 40 V RST and ENABLE = 5.0 V No output loads on Gate Drive Pins, No PWM No output loads on Gate Drive Pins, 20 kHz, 50% Duty Cycle VPWR Supply Current, VPWR = VSUP = 40 V RST and ENABLE = 5.0 V No output loads on Gate Drive Pins, No PWM, Outputs initialized Output Loads = 620 nC per FET, 20 kHz PWM(11) Sleep State Supply Current, RST = 0 V VSUP = 40 V VPWR = 40 V Sleep State Output Gate Voltage IG < 100 A Trickle Charge Pump (Bootstrap Voltage) VSUP = 14 V Bootstrap Diode Forward Voltage at 10 mA VDD INTERNAL REGULATOR VDD Output Voltage, VPWR = 8 to 40 V, C = 0.47 F(12) External Load IDD_EXT = 0 to 1.0 mA Internal VDD Supply Current, VDD = 5.5 V, No External Load VLS REGULATOR Peak Output Current, VPWR = 16 V, VLS = 10 V Linear Regulator Output Voltage, IVLS = 0 to 60 VLS Disable Threshold(14) mA(13) IPEAK VLS VTHVLS 350 13.5 7.5 600 15 8.0 800 17 8.5 mA V V IDD VDD 4.5 - - - 5.5 12 mA V VF VBoot 22 - 28 - 32 1.2 V ISUP IPWR VGATESS - - 1.3 V - - 14 56 30 100 V - - 11 - 20 95 A IPWR_ON - - 1.0 - - 10 mA VPWR_ST ISUP - 6.0 8.0 V mA Symbol Min Typ Max Unit Notes 10. Operation with the Charge Pump is recommended when minimum system voltage could be less than 14 V. VPWR must exceed this threshold in order for the Charge Pump and VDD regulator to startup and drive VPWR to > 8.0 V. Once VPWR exceeds 8.0 V, the circuits will continue to operate even if system voltage drops below 6.0 V. 11. This parameter is guaranteed by design. It is not production tested. 12. Minimum external capacitor for stable VDD operation is 0.47 F. 13. 14. Recommended external capacitor for the VLS regulator is 2.2 F low ESR at each pin VLS and VLS_CAP. When VLS is less than this value, the outputs are disabled and HOLDOFF circuits are active. Recovery is automatic when VLS rises above this threshold again. A filter delay of approximately 700 ns on the comparator output eliminates responses to spurious transients on VLS. 33937 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic CHARGE PUMP Charge Pump High Side Switch On Resistance Low Side Switch On Resistance Regulation Threshold Difference(15), (17) Charge Pump Output Voltage(16), (17) IOUT = 40 mA, 6.0 V < VSYS < 8.0 V IOUT = 40 mA, VSYS > = 8.0 V GATE DRIVE High Side Driver On Resistance (Sourcing) VPWR = VSUP = 16 V, -40C TA 25C VPWR = VSUP = 16 V, 25C < TA 135C High Side Driver On Resistance (Sinking) VPWR = VSUP = 16 V High Side Current Injection Allowed Without Malfunction(17), (18) Low Side Driver On Resistance (Sourcing) VPWR = VSUP = 16 V, -40C TA 25C VPWR = VSUP = 16 V, 25C < TA 135C Low Side Driver On-Resistance (Sinking) VPWR = VSUP = 16 V Low Side Current Injection Allowed Without Malfunction(17), (18) Gate Source Voltage, VPWR = VSUP = 40 V High Side, IGATE = 0(19) Low Side, IGATE = 0 High Side Gate Drive Output Leakage Current, Per Output(20) VGS_H VGS_L IHS_LEAK 13 13 - 14.8 15.4 - 16.5 17 18 A ILS_INJ RDS(ON)_L_SINK - - - - 3.0 0.5 V IHS_INJ RDS(ON)_L_SRC - - - - 6.0 8.5 RDS(ON)_H_SINK - - - - 3.0 0.5 A RDS(ON)_H_SRC - - - - 6.0 8.5 RDS(on)_HS RDS(on)_LS VTHREG VCP 8.5 12 9.5 - - - - - 250 6.0 5.0 500 10 9.4 900 mV V Symbol Min Typ Max Unit Notes 15. When VLS is this amount below the normal VLS linear regulation threshold, the charge pump is enabled. 16. VSYS is the system voltage on the input to the charge pump. With recommended external components (1.0 F, MUR 120 diode). The Charge Pump is designed to supply the gate currents of a system with 100 A FETs in a 12 V application. 17. This parameter is a design characteristic, not production tested. 18. Current injection only occurs during output switch transitions. The IC is immune to specified injected currents for a duration of approximately 1.0s after an output switch transition. 1.0 s is sufficient for all intended applications of this IC. 19. If a slightly higher gate voltage is required, larger bootstrap capacitors are required. At high duty cycles, the bootstrap voltage may not recover completely, leading to a higher output on-resistance. This effect can be minimized by using low ESR capacitors for the bootstrap and the VLS capacitors. 20. A small internal charge pump will supply up to 30 A nominal to compensate for leakage on the High Side FET gate output and maintain voltages after bootstrap events. It is not intended for external components to be connected to the High Side FET gate, but small amounts of additional leakage can be accommodated. See Figures 11 through 14 for typical load margins. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic OVER-CURRENT COMPARATOR Common Mode Input Range(22) Input Offset Voltage Over-current Comparator Threshold Hysteresis(21) Output Voltage High Level at IOH = -500 A Low Level at IOL = 500 A HOLD OFF CIRCUIT Hold Off Current (At Each GATE Pin) 3.0 V < VSUP < 40 V(23) PHASE COMPARATOR High Level Input Voltage Threshold Low Level Input Voltage Threshold High Level Output Voltage at IOH = -500 A Low Level Output Voltage at IOL = 500 A High Side Source Input Resistance(21), (26) DESATURATION DETECTOR Desaturation Detector Threshold(24) CURRENT SENSE AMPLIFIER Recommended External Series Resistor (See Figure 9) Recommended External Feedback Resistor (See Figure Limited by the Output Voltage Dynamic Range Maximum Input Differential Voltage (See Figure 9) VID = VAMP_P - VAMP_N Input Common Mode Range(21), (25) Input Offset Voltage RS = 1.0 k, VCM = 0.0 V Input Offset Voltage Drift(21) Input Bias Current VCM = 2.0 V VOS/T Ib -200 - +200 VCM VOS -15 - - -10 +15 - V/C nA VID -800 -0.5 - - +800 3.0 V mV 9)(27) RS RFB 5.0 - 15 mV - 1.0 - k k VDES_TH 1.2 1.4 1.6 V VIH_TH VIL_TH VOH VOL RIN 0.5 VSUP 0.3 VSUP 0.85 VDD - - - - - - 40 0.65 VSUP 0.45 VSUP VDD 0.5 - V V V V k IHOLD 10 - 300 A VOH VOL 0.85 VDD - - - VDD 0.5 VCM VOS_OC VOC_HYST 2.0 -50 50 - - VDD-0.02 50 300 V mV mV V Symbol Min Typ Max Unit Notes 21. This parameter is a design characteristic, not production tested. 22. As long as one input is in the common mode range there is no phase inversion on the output. 23. The hold off circuit is designed to operate over the full operating range of VSUP. The specification indicates the conditions used in production test. Hold off is activated at VTHRST or VTHVLS. 24. 25. 26. 27. Desaturation is measured as the voltage drop below VSUP, thus the threshold is compared to the drain-source voltage of the external High Side FET. See Figure 5. As long as one input is within VCM the output is guaranteed to have the correct phase. Exceeding the common mode rails on one input will not cause a phase inversion on the output. Input resistance is impedance from High Side source and is referenced to VSS. Approximate tolerance is 20%. The current sense amplifier is unity gain stable with a phase margin of approximately 45. See Figure 10. 33937 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic CURRENT SENSE AMPLIFIER (CONTINUED) Input Offset Current IOS = IAMP_P - IAMP_N Input Offset Current Drift (28) Output Voltage High Level with RLOAD = 10 k to VSS Low Level with RLOAD = 10 k to VDD Differential Input Resistance Output Short-circuit Current Common Mode Input Capacitance at 10 kHz Common Mode Rejection Ratio at DC CMRR = 20*Log ((VOUT_diff/VIN_diff) * (VIN_CM/VOUT_CM)) Large Signal Open Loop Voltage Gain (DC) (28), (29) Nonlinearity (28), (29) RL = 1.0 k, CL = 500 pF, 0.3 < VO < 4.8 V, Gain = 5.0 to 15 AOL NL -1.0 - +1.0 (28), (29) Symbol Min Typ Max Unit IOS -80 IOS/T VOH VOL RI ISC CI CMRR 60 - 80 78 - - - VDD-0.2 - 1.0 5.0 - - 40 - - - - - +80 - VDD 0.2 - - 10 nA pA/C V M mA pF dB dB % Notes 28. This parameter is a design characteristic, not production tested. 29. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic SUPERVISORY AND CONTROL CIRCUITS Logic Inputs (Px_LS, Px_HS, EN1, EN2) (31) High Level Input Voltage Threshold Low Level Input Voltage Threshold Logic Inputs (SI, SCLK, CS) (30), (31) Symbol Min Typ Max Unit V VIH VIL VIH VIL VIHYS 100 IINPD 8.0 IINPU 10 CIN - VTH_RST RRST 40 VTHRST VSOH 0.9 VDD VSOL - ISO_LEAK_T -1.0 CSO_T - VOH 0.85 VDD VOL - - 0.5 - VDD V 15 - V - 1.0 pF - 0.1 VDD A - - V 3.4 60 4.0 85 4.5 V V 1.0 15 - - 2.1 V k - 25 A pF - 18 250 450 A - 0.9 - 0.9 - - - - 2.1 - V 2.1 - mV High Level Input Voltage Threshold Low Level Input Voltage Threshold Input Logic Threshold Hysteresis (30) Inputs Px_LS, SI, SCLK, CS, Px_HS, EN1, EN2 Input Pull-down Current, (Px_LS, SI, SCLK, EN1, EN2) 0.3 VDD VIN VDD Input Pull-up Current, (CS, Px_HS) (32) 0 VIN 0.7 VDD Input Capacitance (30) 0.0 V VIN 5.5 V RST Threshold (33) RST Pull-down Resistance 0.3 VDD VIN VDD Power-ON RST Threshold, (VDD Falling) SO High Level Output Voltage IOH = 1.0 mA SO Low Level Output Voltage IOL = 1.0 mA SO Tri-state Leakage Current CS = 0.7 VDD, 0.3 VDD = VSO = 0.7 VDD SO Tri-state Capacitance (30), (34) 0.0 V VIN 5.5 V INT High Level Output Voltage IOH = -500 A INT Low Level Output Voltage IOL = 500 A THERMAL WARNING Thermal Warning Temperature (30), (35) Thermal Hysteresis (30) Notes 30. This parameter is guaranteed by design, not production tested. 31. Logic threshold voltages derived relative to a 3.3 V 10% system. 32. Pull-up circuits will not allow back biasing of VDD. 33. 34. 35. TWARN THYST 150 8.0 170 10 185 12 C C There are two elements in the RST circuit: 1) one generally lower threshold enables the internal regulator; 2) the second removes the reset from the internal logic. This parameter applies to the OFF state (tri-stated) condition of SO is guaranteed by design but is not production tested. The Thermal Warning circuit does not force IC shutdown above this temperature. It is possible to set a bit in the MASK register to generate an interrupt when overtemperature is detected, and the status bit will always indicate if any of the three individual Thermal Warning circuits in the IC sense a fault. 33937 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic INTERNAL REGULATORS VDD Power-Up Time (Until INT High) 8.0 V VPWR (36) VLS Power-Up Time 16 V VPWR (37) CHARGE PUMP Charge Pump Oscillator Frequency Charge Pump Slew GATE DRIVE High Side Turn On Time(39) Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, (Figure 7) High Side Turn On Delay(40) Delay from Command to 1.0 V, (Figure 7) High Side Turn Off Time(39) Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, (Figure 8) High Side Turn Off Delay(40) Delay from Command to 10 V, (Figure 8) Low Side Turn On Time(39) Transition Time from 1.0 to 10 V, Load: C = 500 pF, Rg = 0, (Figure 7) Low Side Turn On Delay(40) Delay from Command to 1.0 V, (Figure 7) Low Side Turn Off Time(39) Transition Time from 10 to 1.0 V, Load: C = 500 pF, Rg = 0, (Figure 8) Low Side Turn Off Delay(40) Delay from Command to 10 V, (Figure 8) Same Phase Command Delay Match(41) Thermal Filter Duration (42) tD_DIFF tDUR tD_OFFL 130 -20 8.0 265 0 - 386 +20 30 ns s tOFFL - 20 35 ns tD_ONL 130 265 386 ns tONL - 20 35 ns tD_OFFH 130 265 386 ns tOFFH - 20 35 ns tD_ONH 130 265 386 ns tONH - 20 35 ns ns Rate(38) FOSC SRCP 90 - 125 100 190 - kHz V/s tPU_VDD - - 2.0 tPU_VDD - - 2.0 ms ms Symbol Min Typ Max Unit Notes 36. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitor on VDD. 37. 38. 39. 40. The power-up time of the IC depends in part on the time required for this regulator to charge up the external filter capacitors on VLS and VLS_CAP. This delay includes the expected time for VDD to rise. The charge pump operating at 12 V VSYS, 1.0F pump capacitor, MUR120 diodes and 47 F filter capacitor. This parameter is guaranteed by characterization, not production tested. These delays include all logic delays except deadtime. All internal logic is synchronous with the internal clock. The total delay includes one clock period for state machine decision block, an additional clock period for FULLON mux logic, input synchronization time and output driver propagation delay. Subtract one clock period for operation in FULLON mode which bypasses the state machine decision block. Synchronization time accounts for up to one clock period of variation. See Figure 6. The maximum separation or overlap of the High and Low Side gate drives, due to propagation delays when commanding one ON and the other OFF simultaneously, is guaranteed by design. The output of the overtemperature comparator goes through a digital filter before generating a warning or interrupt. 41. 42. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic GATE DRIVE (CONTINUED) Duty Cycle (43), (44) 100% Duty Cycle Duration (43), (44) (45) Symbol Min Typ Max Unit tDC tDC tMAX 0.0 - 10.2 - - 15 96 Unlimited 19.6 % s s Maximum Programmable Deadtime OVER-CURRENT COMPARATOR Over-current Protection Filter Time Rise Time (OC_OUT) 10% - 90% CL = 100 pF Fall Time (OC_OUT) 90% - 10% CL = 100 pF tOC tROC 0.9 10 - - 3.5 240 s ns tFOC 10 - 200 ns DESATURATION DETECTOR AND PHASE COMPARATOR Phase Comparator Propagation Delay Time to 50% of VDD; CL 100 pF Rising Edge Delay Falling Edge Delay Phase Comparator Match (Prop Delay Mismatch of Three Phases) CL = 100 pF (43) ns tR tF tMATCH - - - - - - 200 350 100 ns Desaturation and Phase Error Blanking Time(46) Desaturation Filter Time (Filter Time is digital) (43) Fault Must be Present for This Time to Trigger CURRENT SENSE AMPLIFIER Output Settle Time to 99% (43), (47) RL = 1.0 k, CL = 500 pF, 0.3 V < VO < 4.8 V, Gain = 5 to 15 tBLANK tFILT 4.7 7.1 9.1 s ns 640 937 1231 tSETTLE - 1.0 2.0 s Notes 43. This parameter is guaranteed by design, not production tested. 44. Maximum duty cycle is actually 100% because there is an internal charge pump to maintain the gate voltage in the 100% on condition. However, in high duty cycle cases, there may not be sufficient time to recharge the bootstrap capacitors during the off time. Large bootstrap capacitors will allow high duty cycles to be obtained for a short time. For applications needing closer to 100% duty cycle, external diodes may optionally be used to provide high peak current charging capability to the bootstrap capacitors. These diodes would be connected between VLS and the Px_BOOTSTRAP pins. In applications with lower gate charge requirements, the maximum duty cycle can also be increased. 45. A Minimum Deadtime of 0.0 can be set via an SPI command. When Deadtime is set via a DEADTIME command, a minimum of 1 clock cycle duration and a maximum of 255 clock cycles is set using the internal time base clock as a reference. Commands exceeding this value limits at this value. 46. Blanking time, tBLANK, is applied to all phases simultaneously when switching ON any output FET. This precludes false errors due to system noise during the switching event. 47. Without considering any offsets such as input offset voltage, internal mismatch and assuming no tolerance error in external resistors. 33937 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic CURRENT SENSE AMPLIFIER (CONTINUED) Output Rise Time to 90% (49) RL = 1.0 k, CL = 500 pF, 0.3 V < VO < 4.8 V, Gain = 5.0 to 15 Output Fall Time to 10% (49) RL = 1.0 k, CL = 500 pF, 0.3 V < VO < 4.8 V, Gain = 5.0 to 15 Slew Rate at Gain = 5.0(48) RL = 1.0 k, CL = 20 pF Phase Margin at Gain = Unity Gain Bandwidth 5.0(48) fM GBW - BWG 2.0 (48) Symbol Min Typ Max Unit tIS_RISE - tIS_FALL - SR(5) 5.0 - - 30 - - - 1.0 - 1.0 s s V/s MHz (48) RL = 1.0 k, CL = 100 pF Bandwidth at Gain = 15 (48) RL = 1.0 k, CL = 50 pF Common Mode Rejection (CMR) VIN_DIF = 0.0 V, RS = 1.0 k RFB = 15 k, VREFIN = 0.0 V CMR = 20*Log(VOUT/VIN_CM) Freq = 100 kHz Freq = 1.0 MHz Freq = 10 MHz SUPERVISORY AND CONTROL CIRCUITS EN1 and EN2 Propagation Delay INT Rise Time CL = 100 pF INT Fall Time CL = 100 pF INT Propagation Time tPROP tRINT tFINT tPROPINT with VIN CMR VIN_CM = 400 mV*sin(2**freq*t) 20 - MHz - - dB 50 40 30 - - - - - - - 10 10 - - - - - 280 250 200 250 ns ns ns ns Notes 48. This parameter is guaranteed by design, not production tested. 49. Rise and fall times are measured from the transition of a step function on the input to 90% of the change in output voltage. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 4. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 8.0 V VPWR = VSUP 40 V, -40C TA 135C, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions, unless otherwise noted. Characteristic SPI INTERFACE TIMING Maximum Frequency of SPI Operation Internal Time Base Internal Time Base drift from value at 25C (50) (50) (50) Symbol Min Typ Max Unit fOP fTB TCTB tLEAD tLAG tSISU tSIHOLD tRSI tFSI (50), (52) (50), (53) - 13 -5.0 100 100 25 25 - - - - - 200 17 - - - - - 5.0 5.0 55 100 80 - 4.0 25 5.0 - - - - - - 100 125 125 - MHz MHz % ns ns ns ns ns ns ns ns ns ns Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) SI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to SI (Required Setup Time) SI, CS, SCLK Signal Rise Time SI, CS, SCLK Signal Fall Time (50), (51) (50) (50) (50), (51) Time from Falling Edge of CS to SO Low-impedance Time from Rising Edge of CS to SO High-impedance Time from Rising Edge of SCLK to SO Data Valid tSOEN tSODIS tVALID (50), (54) (50) Time from Rising Edge of CS to Falling Edge of the next CS Notes 50. 51. 52. 53. 54. tDT This parameter is guaranteed by design, not production tested. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for valid output status data to be available on SO pin. Time required for output states data to be terminated at SO pin. Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load. 33937 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS CS 0.2 VDD tL EA D ttLA G LAG SCLK 0 .7 VD D 0 .2 VD D tDI(SU) tSIHOLD tSISU tDI(HO LD) SI 0 .7 VD D 0 .2 VD D MSB in tSOEN tDO(E N) tV A LI D 0 .7 VD D 0 .2 VD D tSODIS tDO (DIS ) SO MSB out LSB out Figure 4. SPI Interface Timing PX_HS PX_LS FROM DELAY TIMER DESATURATION FAULT Figure 5. Desaturation Blanking and Filtering Detail B PX_HS D CLK DEADTIME CONTROL Q STATE MACHINE MUX D CLK Q A OUT D CLK Q PX_HS_G PX_HS_S PX_LS D CLK Q 1ST PULSE D CLK Q A OUT MUX B D CLK Q PX_LS_G EN1 EN2 RST Figure 6. Deadtime Control Delays 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS 50% Px_HS 10V tD_ONH 1 .0 V tONH Px_HS _G 50% Px_LS 10V tD_ONL 1.0V tONL Px_LS_G Figure 7. Driver Turn-On Time and Turn-On Delay 50% Px_HS 10V Px_HS_G tD_OFFH 1 .0 V tOFFH 50% Px_ LS 1 0V tD_OFFL 1.0V tOFFL Px_LS_G Figure 8. Driver Turn-off Time and Turn-off Delay 33937 18 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS RE F To P rotection Circuits R FB P AMP_P + V ID AMP_N OC_TH AMP_O UT R FBN Rs + V IN Rs R sens e Figure 9. Current Amplifier and Input Waveform (VIN Voltage Across RSENSE) Figure 10. Typical Amplifier Open-loop Gain and Phase Margin vs Frequency 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS Typical Trickle Charge Pump Supply Voltage and Margin 24 12 20 10 16 Margin at +3V (uA) 8 12 6 8 4 4 2 0 5 10 15 20 HS_S/Vsup (V) I dV 25 30 35 40 0 Figure 11. Typical Trickle Charge Pump Supply Voltage and Current Margin vs Supply Voltage Trickle Charge Pump Load Margin and Supply Voltage at HS_S=Vsup=14V 17 16 15 14 Load Margin at +3V (uA) 13 12 11 10 9 8 7 20 40 60 80 100 Tj (C) I dV 120 140 160 13 12 11 10 9 8 7 6 5 4 3 180 Vcboot-VHS_S at 2.5uA load (dV) Figure 12. Typical Voltage and Load Margin For Increasing Junction Temperature at 14 V on HS_S 33937 20 Analog Integrated Circuit Device Data Freescale Semiconductor Vcboot-VHS_S at 2.5uA load (dV) ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS Trickle Charge Pump Load Margin and Supply Voltage at HS_S=Vsup=24V 9 8.5 8 7.5 Load Margin at +3V (uA) 7 6.5 6 5.5 5 4.5 4 20 40 60 80 100 Tj (C) I dV 120 140 160 13 12 11 10 9 8 7 6 5 4 3 180 Vcboot-VHS_S at 2.5uA load (dV) Figure 13. Typical Voltage and Load Margin For Increasing Junction Temperature at 24 V on HS_S Trickle Charge Pum p Load Margin and Supply Voltage at HS_S=Vsup=36V 9 8 7 Load Margin at +3V (uA) 6 5 4 3 2 1 0 20 40 60 80 100 Tj (C) I dV 120 140 160 12 11 10 9 8 7 6 5 4 3 180 Vcboot-VHS_S at 2.5uA load (dV) Figure 14. Typical Voltage and Load Margin For Increasing Junction Temperature at 36 V on HS_S 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 21 FUNCTIONAL DESCRIPTIONS INTRODUCTION FUNCTIONAL DESCRIPTIONS INTRODUCTION The 33937 provides an interface between an MCU and the large FETs used to drive three phase loads. A typical load FET may have an on resistance of 4.0 m or less and could require a gate charge of over 400 nC to fully turn on. The IC can operate in automotive 12 to 42 V environments. Because there are so many methods of controlling three phase systems, the IC enforces few constraints on driving the FETs. It does provide deadtime (cross-over) blanking and logic, both of which can be overridden, ensuring both FETs in a phase are not simultaneously enabled. An SPI port is used to configure the IC modes. FUNCTIONAL PIN DESCRIPTION PHASE A (PHASEA) This pin is the totem pole output of the Phase A comparator. This output is low when the voltage on Phase A High Side source (source of the High Side load FET) is less than 50 percent of VSUP. If the charge pump is not required this pin may be left floating. VSUP INPUT (VSUP) The supply voltage pin should be connected to the common connection of the High Side FETs. It is the reference bias for the Phase Comparators and Desaturation Comparator. It is also used to provide power to the internal steady state trickle charge pump and to energize the hold off circuit. POWER GROUND (PGND) This pin is power ground for the charge pump. It should be connected to VSS, however routing to a single point ground on the PCB may help to isolate charge pump noise. ENABLE 1 AND ENABLE 2 (EN1, EN2) Both of these logic signal inputs must be high to enable any gate drive output. When either or both are low, the internal logic (SPI port, etc.) still functions normally, but all gate drives are forced off (external power FET gates pulled low). The signal is asynchronous. When EN1 and EN2 return high to enable the outputs, each LS driver must be pulsed on before the corresponding HS driver can be commanded on. This ensures that the bootstrap capacitors are charged. PHASE B (PHASEB) This pin is the totem pole output of the Phase B comparator. This output is low when the voltage on Phase B High Side source (source of the High Side load FET) is less than 50 percent of VSUP. PHASE C (PHASEC) This pin is the totem pole output of the Phase C comparator. This output is low when the voltage on Phase C High Side source (source of the High Side load FET) is less than 50 percent of VSUP. RESET (RST) When the reset pin is low the integrated circuit (IC) is in a low power state. In this mode all outputs are disabled, internal bias circuits are turned off, and a small pull-down current is applied to the output gate drives. The internal logic will be reset within 77 ns of RESET going low. When RST is low, the IC will consume minimal current. PHASE A HIGH SIDE INPUT (PA_HS) This input logic signal pin enables the High Side Driver for Phase A. The signal is active low, and is pulled up by an internal current source. PHASE A LOW SIDE INPUT (PA_LS) This input logic signal pin enables the Low Side Driver for Phase A. The signal is active high, and is pulled down by an internal current sink. CHARGE PUMP OUT (PUMP) This pin is the switching node of the charge pump circuit. The output of the internal charge pump support circuit. When the charge pump is used, it is connected to the external pumping capacitor. This pin may be left floating if the charge pump is not required. VDD VOLTAGE REGULATOR (VDD) VDD is an internally generated 5.0 V supply. The internal regulator provides continuous power to the IC and is a supply reference for the SPI port. A 0.47 F (min) decoupling capacitor must be connected to this pin. This regulator is intended for internal IC use and can supply only a small (1.0 mA) external load current. CHARGE PUMP INPUT (VPUMP) This pin is the input supply for the charge pump circuit. When the charge pump is required, this pin should be connected to a polarity protected supply. This input should never be connected to a supply greater than 40 V. 33937 22 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTIONS INTRODUCTION A power-on-reset (POR) circuit monitors this pin and until the voltage rises above the threshold, the internal logic will be reset; driver outputs will be tri-stated and SPI communication disabled. The VDD regulator can be disabled by asserting the RST signal low. The VDD regulator is powered from the VPWR pin. PHASE C HIGH SIDE INPUT (PC_HS) This input logic pin enables the High Side Driver for Phase C. This signal is active low, and is pulled up by an internal current source. AMPLIFIER OUTPUT (AMP_OUT) This pin is the output for the current sensing amplifier. It is also the sense input to the over-current comparator. PHASE B HIGH SIDE CONTROL INPUT (PB_HS) This pin is the input logic signal, enabling the High Side driver for Phase B. The signal is active low, and is pulled up by an internal current source. AMPLIFIER INVERTING INPUT (AMP_N) The inverting input to the current sensing amplifier. PHASE B LOW SIDE INPUT (PB_LS) This pin is the input logic signal, enabling the Low Side driver for Phase B. The signal is active high, and is pulled down by an internal current sink. AMPLIFIER NON-INVERTING INPUT (AMP_P) The non-inverting input to the current sensing amplifier. OVER-CURRENT COMPARATOR OUTPUT (OC_OUT) The over-current comparator output is a totem pole logic level output. A logic high indicates an over-current condition. INTERRUPT (INT) The Interrupt pin is a totem pole logic output. When a fault is detected, this pin will pull high until it is cleared by executing the Clear Interrupt command via the SPI port. The faults capable of causing an interrupt can be masked via the MASK0 and MASK1 SPI registers to customize the response. OVER-CURRENT COMPARATOR THRESHOLD (OC_TH) This input sets the threshold level of the over-current comparator. CHIP SELECT (CS) Chip select is a logic input that frames the SPI commands and enables the SPI port. This signal is active low, and is pulled up by an internal current source. VOLTAGE SOURCE SUPPLY (VSS) VSS is the ground reference for the logic interface and power supplies. SERIAL IN (SI) The Serial In pin is used to input data to the SPI port. Clocked on the falling edge of SCLK, it is the most significant bit (MSB) first. This pin is pulled down by an internal current sink. GROUND (GND0,GND1) These two pins are connected internally to VSS by a 1.0 resistor. They provide device substrate connections and also the primary return path for ESD protection. VLS REGULATOR CAPACITOR (VLS_CAP) This connection is for a capacitor which will provide a lowimpedance for switching currents on the gate drive. A low ESR decoupling capacitor, capable of sourcing the pulsed drive currents must be connected between this pin and VSS. Use the 33937A to avoid the CAUTION on page 27 for capacitances greater than 3.5 F. This is the same DC node as VLS, but it is physically placed on the opposite end of the IC to minimize the source impedance to the gate drive circuits. SERIAL CLOCK (SCLK) This logic input is the clock is used for the SPI port. The SCLK typically runs at 3.0 MHz (up to 5.0 MHz) and is pulled down by an internal current sink. SERIAL OUT (SO) Output data for the SPI port streams from this pin. It is tristated until CS is low. New data appears on rising edges of SCLK in preparation for latching by the falling edge of SCLK on the master. PHASE C LOW SIDE SOURCE (PC_LS_S) The phase C Low Side source is the pin used to return the gate currents from the Low Side FET. Best performance is realized by connecting this node directly to the source of the Low Side FET for phase C. PHASE C LOW SIDE INPUT (PC_LS) This input logic pin enables the Low Side Driver for Phase C. This pin is an active high, and is pulled down by an internal current sink. PHASE C LOW SIDE GATE (PC_LS_G) This is the gate drive for the phase C Low Side output FET. It provides high current through a low impedance to turn on 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 23 FUNCTIONAL DESCRIPTIONS INTRODUCTION and off the Low Side FET.. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has also been designed to resist the influence of negative currents. on or off. The gate voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the influence of negative currents. PHASE C HIGH SIDE SOURCE (PC_HS_S) The source connection for the phase C High Side output FET is the reference voltage for the gate drive on the High Side FET and also the low voltage end of the bootstrap capacitor. PHASE B BOOTSTRAP (PB_BOOT) This is the bootstrap capacitor connection for phase B. A capacitor connected between PC_HS_S and this pin provides the gate voltage and current to drive the external FET gate. Typically, the boostrap capacitor selection is 10 to 20 times the gate capacitance. The voltage across this capacitor is limited to about 15 V. Use the 33937A to avoid the CAUTION on page 27 for bootstrap capacitances greater than 100 nF. PHASE C HIGH SIDE GATE (PC_HS_G) This is the gate drive for the phase C High Side output FET. This pin provides the gate bias to turn the external FET on or off. The gate voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the influence of negative currents. PHASE A LOW SIDE SOURCE (PA_LS_S) The phase A Low Side source is the pin used to return the gate currents from the Low Side FET. Best performance is realized by connecting this node directly to the source of the Low Side FET for phase A. PHASE C BOOTSTRAP (PC_BOOT) This is the bootstrap capacitor connection for phase C. A capacitor connected between PC_HS_S and this pin provides the gate voltage and current to drive the external FET gate. Typically, the boostrap capacitor selection is 10 to 20 times the gate capacitance. The voltage across this capacitor is limited to about 15 V. Use the 33937A to avoid the CAUTION on page 27 for bootstrap capacitances greater than 100 nF. PHASE A LOW SIDE GATE (PA_LS_G) This is the gate drive for the phase A Low Side output FET. It provides high current through a low impedance to turn on and off the Low Side FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has also been designed to resist the influence of negative currents. PHASE B LOW SIDE SOURCE (PB_LS_S) The phase B Low Side source is the pin used to return the gate currents from the Low Side FET. Best performance is realized by connecting this node directly to the source of the Low Side FET for phase B. PHASE A HIGH SIDE SOURCE (PA_HS_S) The source connection for the phase A High Side output FET is the reference voltage for the gate drive on the High Side FET and also the low voltage end of the bootstrap capacitor. PHASE B LOW SIDE GATE (PC_LS_G) This is the gate drive for the phase B Low Side output FET. It provides high current through a low impedance to turn on and off the Low Side FET. A low-impedance drive ensures transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FET. This output has also been designed to resist the influence of negative currents. PHASE A HIGH SIDE GATE (PA_HS_G) This is the gate drive for the phase A High Side output FET. This pin provides the gate bias to turn the external FET on or off. The gate voltage is limited to about 15 V above the FET source voltage. A low-impedance drive is used, ensuring transient currents do not overcome an off-state driver and allow pulses of current to flow in the external FETs. This output has also been designed to resist the influence of negative currents. PHASE B HIGH SIDE SOURCE (PB_HS_S) The source connection for the phase B High Side output FET is the reference voltage for the gate drive on the High Side FET and also the low voltage end of the bootstrap capacitor. PHASE A BOOTSTRAP (PA_BOOT) This is the bootstrap capacitor connection for phase A. A capacitor connected between PC_HS_S and this pin provides the gate voltage and current to drive the external FET gate. Typically, the boostrap capacitor selection is 10 to 20 times the gate capacitance. The voltage across this capacitor is limited to about 15 V. Use the 33937A to avoid the CAUTION on page 27 for bootstrap capacitances greater than 100 nF. PHASE B HIGH SIDE GATE (PB_HS_G) This is the gate drive for the phase B High Side output FET. This pin provides the gate bias to turn the external FET 33937 24 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTIONS INTRODUCTION VLS REGULATOR (VLS) VLS is the gate drive power supply regulated at approximately 15 V. This is an internally generated supply from VPWR. It is the source for the Low Side gate drive voltage, and also the High Side bootstrap source. A low ESR decoupling capacitor, capable of sourcing the pulsed drive currents, must be connected between this pin and VSS. Use the 33937A to avoid the CAUTION on page 27 for capacitances greater than 3.5 F. well as supplying power to the Low Side gate drivers and the VDD regulator. An internal regulator regulates the actual gate voltages. This pin can be connected to system battery voltage if power dissipation is not a concern. EXPOSED PAD (EP) The primary function of the Exposed Pad is to conduct heat out of the device. This pad may be connected electrically to the substrate of the device.The device will perform as specified with the Exposed Pad un-terminated (floating). However, it is recommended that the Exposed Pad be terminated to pin 29 (VSS) and the system ground. VPWR INPUT (VPWR) VPWR is the power supply input for VLS and VDD. Current flowing into this input recharges the bootstrap capacitors as 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC33937 - Functional Block Diagram Integrated Supply Main Charge Pump 5V Regulator Trickle Charge Pump VLS Regulator High Side and Low Side Output Pre-drivers Sensing & Protection Hold-off Temperature Current Sense Over-current Logic & Control Fault Register Phase Control Dead Time Mode Control Under-voltage De-sat Phase SPI Communication Integrated Supply Sensing & Protection Logic & Control Drivers Figure 15. Functional Internal Block Description 12 s. Calibration of the delay, because of internal IC All functions of the IC can be described as the following variations, is performed via the SPI. five major functional blocks: * Enabling of simultaneous operation of High Side and * Logic Inputs and Interface Low Side FETs--Normally, both FETs would not be * Bootstrap Supply enabled simultaneously. However, for certain applications * Low Side Drivers where the load is connected between the High Side and * High Side Drivers Low Side FETs, this could be advantageous. If this mode * Charge Pump is enabled, the blanking time delay will be disabled. A sequence of commands may be required to enable this LOGIC INPUTS AND INTERFACE function to prevent inadvertent enabling. In addition, this This section contains the SPI port, control logic, and shootcommand can only be executed once after reset to enable through timers. or disable simultaneous turn-on. * Setting of various operating modes of the IC and The IC logic inputs have Schmitt trigger inputs with enabling of interrupt sources. hysteresis. Logic inputs are 3.0 V compatible. The logic The 33937 allows different operating modes to be set and outputs are driven from the internal supply of approximately locked by an SPI command (FULLON, Desaturation Fault, 5.0 V. Zero Deadtime). SPI commands can also determine how The SPI registers and functionality is described completely the various faults are (or are not) reported. in the LOGIC COMMANDS AND REGISTERS section of this * Read back of internal registers. document. SPI functionality includes the following: The status of the 33937 Status Registers can be read back * Programming of deadtime delay--This delay is by the Master (DSP or MCU). adjustable in approximately 50 ns steps from 0 ns to 33937 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL INTERNAL BLOCK DESCRIPTION The Px_HS and Px_LS logic inputs are edge sensitive. This means the leading edge on an input will cause the complementary output to immediately turn off and the selected one to turn on after the deadtime delay as illustrated in Figure 16. The deadtime delay timer starts when the corresponding FET was commanded off (see Figure 6 and Figure 16). ensures the impedance of the driver remains low, even during periods of reduced current. Current limit is blanked immediately after subsequent input state change in order to ensure device stays off during dV/dt transients. HIGH SIDE DRIVERS These three drivers switch the voltage across the bootstrap capacitor to the external High Side FETs. The circuits provide a low-impedance drive to the gate, ensuring the FETs remain off in the presence of high dV/dt transients on their sources. Further, these output drivers isolate the other portions of the IC from currents capable of being injected into the substrate due to rapid dV/dt transients on the FETs. The High Side drivers deliver power from their bootstrap capacitor to the gate of the external High Side FET, thus turning the High Side FET on. The High Side driver uses a level shifter, which allows the gate of the external High Side FET to be turned off by switching to the High Side FET source. The gate supply voltage for the High Side drivers is obtained from the bootstrap supply, so, a short time is required after the application of power to the IC to charge the bootstrap capacitors. To ensure this occurrence, the internal control logic will not allow a High Side switch to be turned on after entering the ENABLE state until the corresponding Low Side switch is enabled at least once. Caution must be exercised after a long period of inactivity of the Low Side switches to verify the bootstrap capacitor is not discharged. It will be charged by activating the Low Side switches for a brief period, or by attaching external bleed resistors from the HS_S pins to GND. CAUTION for 33937 only (Use the 33937A to avoid this CAUTION) PA _HS PA_LS De adt ime De lay PA_HS_G PA_LS_G Figure 16. Edge Sensitive Logic Inputs (Phase A) BOOTSTRAP SUPPLY (VLS) This is the portion of the IC providing current to recharge the bootstrap capacitors. It also supplies the peak currents required for the Low Side gate drivers. The power for the gate drive circuits is provided by VLS which is supplied from the VPWR pin. This pin can be connected to system battery voltage and is capable of withstanding up to the full load dump voltage of the system. However, the IC only requires a low-voltage supply on this pin, typically 13 to 16 V. Higher voltages on this pin will increase the IC power dissipation. In 12 V systems the supply voltage can fall as low as 6.0 V. This limits the gate voltage capable of being applied to the FETs and reduces system performance due to the higher FET on-resistance. To allow a higher gate voltage to be supplied, the IC also incorporates a charge pump. The switches and control circuitry are internal; the capacitors and diodes are external (see Figure 22). LOW SIDE DRIVERS These three drivers turn on and off the external Low Side FETs. The circuits provide a low-impedance drive to the gate, ensuring the FETs remain off in the presence of high dV/dt transients on their drains. Additionally, these output drivers isolate the other portions of the IC from currents capable of being injected into the substrate due to rapid dV/dt transients on the FET drains. Low Side drivers switch power from VLS to the gates of the Low Side FETs. The Low Side drivers are capable of providing a typical peak current of 2.0 A. This gate drive current may be limited by external resistors in order to achieve a good trade-off between the efficiency and EMC (Electro-Magnetic Compatibility) compliance of the application. the Low Side driver uses High Side PMOS for turn on and Low Side isolated LDMOS for turn off. The circuit Using the 33937 in applications which use large value bootstrap capacitors requires extra care to insure the transient induced when charging fully depleted capacitors does not cause an unintended power on reset. The 33937A has been modified to eliminate the need for these special considerations. Factors which affect the sensitivity to this effect are, bootstrap capacitor size, VLS filter capacitor size, VLS voltage and the junction temperature. The effect is more pronounced for greater values of these parameters. It is also more pronounced if all phases charge depleted capacitors simultaneously. For balanced capacitance on VLS and VLS_CAP of greater than 3.5 F (total of 7.0 F VLS filtering), 1.2 F bootstrap capacitance on each phase could cause a POR at room temperature with VLS at 13 V. At the worst case conditions of 15.4 V VLS voltage and 150C junction temperature, with the same total VLS capacitance of 7.0 F, approximately 0.3 F total (0.1F each) on Px_BOOT could cause the same effect. Since this characteristic is intrinsic to the bootstrap diode integrated on the device, a valid solution to prevent an undesired reset during initialization would be to use external diodes between VLS and the Px_BOOT pin. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL INTERNAL BLOCK DESCRIPTION In order to achieve a 100% duty cycle operation of the High Side external FETs, a fully integrated trickle charge pump provides the charge necessary to maintain the external FET gates at fully enhanced levels. The trickle charge pump has limited ability to supply external leakage paths while performing it's primary function. The graphs in Figures 11 through 14 beginning on page 20 show the typical margin for supplying external current loads. These limits are based on maintaining the voltage at CBOOT at least 3.0 V greater than the voltage on the HS_S for that phase. If this voltage differential becomes less than 3.0 V, the corresponding high side FET will most likely not remain fully enhanced and the high side driver may malfunction due to insufficient bias voltage between CBOOT and HS_S. The slew rate of the external output FET is limited by the driver output impedance, overall (external and internal) gate resistance and the load capacitance. To ensure the Low Side FET is not turned on by a large positive dV/dt on the drain of the Low Side FET, the turn-on slew rate of the High Side should be limited. If the slew rate of the High Side is limited by the gate-drain capacitance of the High Side FET, then the displacement current injected into the Low Side gate drive output will be approximately the same value. Therefore, to ensure the Low Side drivers can be held off, the voltage drop across the Low Side gate driver must be lower than the threshold voltage of the Low Side FET (see Figure 17). Similarly, during large negative dV/dt, the High Side FET will be able to remain off if its gate drive Low Side switch, develops a voltage drop less than the threshold voltage of the High Side FET. The gate drive Low Side switch discharges the gate to the source. Additionally, during negative dV/dt the Low Side gate drive could be forced below ground. The Low Side FETs must not inject detrimental substrate currents in this condition. The occurrence of these cases depends on the polarity of the load current during switching. 33927 Px_HS_S Low -Side Driver Zo CDG iCDG G Px_LS_G Rg CGS Px_LS_S + D Phase x Output Discrete FET Package CDS VLS LS Control S Phase Return Px_HS_G Deadtime Px_LS_G VSUP Phase x Output Voltage dV/dt -VD Figure 17. Positive DV/dt Transient DRIVER FAULT PROTECTION The 33937 IC integrates several protection mechanisms against various faults. The first of them is the Current Sense Amplifier with the Over-current Comparator. These two blocks are common for all three driver phases. Current Sense Amplifier This amplifier is usually connected as a differential amplifier (see Figure 9). It senses a current flowing through the external FETs as a voltage across the current sense resistor RSENSE. Since the amplifier common mode range does not extend below ground, it is necessary to use an external reference to permit measuring both positive and negative currents. The amplifier output can be monitored directly (e.g. by the microcontroller's ADC) at the AMP_OUT pin, providing the means for closed loop control with the 33937. The output voltage is internally compared with the Overcurrent Comparator threshold voltage (see Figure 22). Over-current Comparator The amplified voltage across RSENSE is compared with the pre-set threshold value by the over-current comparator input. If the Current Sense Amplifier output voltage exceeds the threshold of the Over-current Comparator it would change the status of its output (OC_OUT pin) and the fault condition would be latched (see Figure 20). The occurrence of this fault would be signalled by the return value of the Status Register 0. If the proper Interrupt Mask has been set, this fault condition will generate an 33937 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL INTERNAL BLOCK DESCRIPTION interrupt - the INT pin will be asserted High. The INT will be held in the High state until the fault is removed, and the appropriate bit in the Status Register 0 is cleared by the CLINT0 command. This fault reporting technique is described in detail in the Logic Commands and Registers section. Desaturation Detector Valid faults are registered in the fault status register, which can be retrieved by way of the SPI. Additional SPI commands will mask the INT flag and disable output stage shutdown, due to desaturation and phase errors. See the Logic Commands and Registers section for details on masking INT behavior and disabling the protective function. The Desaturation Detector is a comparator integrated into the output driver of each phase channel. It provides an additional means to protect against "Short-to-Ground" fault condition when the output node gets shorted to the supply voltage (short across the High Side FET). V SUP 3x T-Lim VLS VSUP Desat. Comp. 1. 4V HS Control High Px_BOOT -Side Driver Px_HS_G + - Phase x Output Shorted to VSUP (High-Side FET Shorted) VSUP 3x T-Lim VLS Px_HS_S VSUP Phase Comp. R R Px_LS_S Phase x Output Px_HS_S Phase x Output Shorted to Ground (Low-Side FET Shorted) High Px_BOOT -Side Driver Px_HS_G LS Control Low -Side Driver Px_LS_G Phase x Output VSUP Desat. Comp. 1.4V HS Control Phase Return + - VLS_CAP To Current Sense Amplif. RSense VSUP Phase Comp. R R LS Control Low -Side Driver Px_LS_G Phase Return Px_HS_G Deadtime Px_LS_G VSUP tBLANK Phase x Output Voltage Shorted to VSUP 0.5VSUP Correct Phase x Output Voltage Px_LS_S To Current Sense Amplif. VLS_CAP RSense Px_HS_G Deadtime Px_LS_G V SUP tBLANK tFILT -VD Fault PHASEx Correct Correct Phase x Output Voltage Phase Error 0.5V SUP Phase x Output Voltage Shorted to Ground -V D PHASEx Phase Error Desaturation Error Figure 19. Short to Supply Detection Phase Comparator Correct Fault Figure 18. Short to Ground Detection When switching from Low Side to High Side, the High Side will be commanded ON after the end of the deadtime. The deadtime period starts when the Low Side is commanded OFF. If the voltage at Px_HS_S is less than 1.4V below VSUP after the blanking time (tBLANK) a desaturation fault is initiated. An additional 1.0 s digital filter is applied from the initiation of the desaturation fault before it is registered, and all phase drivers are turned OFF (Px_HS_G clamped to Px_HS_S and Px_LS_G clamped to Px_LS_S). If the desaturation fault condition clears before the filter time expires, the fault is ignored and the filter timer resets. Faults could also be detected as Phase Errors. A phase error is generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. A phase error is detected by a Phase Comparator. The Phase Comparator compares the voltage at the Px_HS_S node with a reference of one half the voltage at the VSUP pin. A High Side phase error (which will also trigger the Desaturation Detector) occurs when the High Side FET is commanded on, and Px_HS_S is still low at the end of the deadtime and blanking time duration. Similarly, a LS phase error occurs when the Low Side FET is commanded on, and the Px_HS_S is still high at the end of the deadtime and blanking time duration. The Phase Error Flag is the triple OR of phase errors from each phase. Each phase error is the OR of the High Side and Low Side phase errors. This flag can generate an interrupt if 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL INTERNAL BLOCK DESCRIPTION the appropriate mask bit is set. The INT will be held in the High state until the fault is removed, and the appropriate bit in the Status Register 0 is cleared by the CLINT1 command. This fault reporting mechanism is described in detail in the Logic Commands and Registers section. HOLD OFF CIRCUIT The IC guarantees the output FETs are turned off in the absence of VDD or VPWR by means of the Hold off circuit. A small current source, generated from VSUP, typically 100 A, is mirrored and pulls all the output gate drive pins low when VDD is less than about 3.0 V, RST is active (low), or when VLS is lower than the VLS_Disable threshold. A minimum of approximately 3.0 V is required on VSUP to energize the Hold off circuit. for VLS includes the charge pump and a linear regulator. The regulation set point for the linear regulator is nominally at 15.34 V. As long as VLS output voltage (VLSOUT) is greater than the VLS analog regulator threshold (VLSATH) minus VTHREG, the charge pump is not active. If VLSOUT < VLSATH - VTHREG the charge pump turns ON until VLSOUT > VLSATH - VTHREG + VHYST VHYST is approximately 200 mV. VLSATH will not interfere with this cycle even when there is overlap in the thresholds, due to the design of the regulator system. The maximum current the charge pump can supply is dependent on the pump capacitor value and quality, the pump frequency (nominally 130 kHz), and the Rdson of the pump FETs. The effective charge voltage for the pump capacitor would be VSYS - 2 * VDIODE. The total charge transfer would then be CPUMP * (VSYS - 2*VDIODE). Multiplying by the switch frequency gives the theoretical current the pump can transfer: FPUMP * CPUMP * (VSYS - 2*VDIODE). NOTE: There is also another smaller, fully integrated charge pump (Trickle Charge Pump - see Figure 2), which is used to maintain the High Side drivers' gate VGS in 100 percent duty cycle modes. CHARGE PUMP The Charge Pump circuit provides the basic switching elements required to implement a charge pump, when combined with external capacitors and diodes for enhanced low voltage operation. When the 33937 is connected per the typical application using the charge pump (see Figure 22), the regulation path 33937 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES RESET AND ENABLE The 33937 has three power modes of operation described in Table 5. There are three global control inputs (RST, EN1, EN2), which together with the status of the VDD and VLS, control the behavior of the IC. The operating status of the IC can be described by the following three modes: Sleep Mode - When RST is low, the IC is in Sleep mode. The current consumption of the IC is at minimum. Table 5. Functions of RST, EN1 and EN2 Pins RST 0 EN1, EN2 xx Mode of Operation (Driver Condition) Sleep Mode - in this mode (low quiescent current) the driver output stage is switched-off with a weak pull-down. All error and SPI registers are cleared. The internal 5.0 V regulator is turned off and VDD is pulled low. All logic outputs except SO are clamped to VSS. Standby Mode - IC fully biased up and all functions are operating, the output drivers actively turn off all of the external FETs (after initialization). The SPI port is functional. Logic level outputs are driven with low impedance. SO is high impedance unless CS is low. VDD, Charge Pump and VLS regulators are all operating. The IC is ready to move to Enable Mode. Enable Mode - (normal operation). Drivers are enabled; output stages follow the input command. After Enable, outputs require a pulse on Px_LS before corresponding HS outputs will turn on in order to charge the bootstrap capacitor. All error pin and register bits are active if detected. * Standby Mode - The RST input is high while one of the Enable inputs is low. The IC is fully biased up and operating, all the external FETs are actively turned off by both High Side and Low Side gate drives. The IC is ready to enter the Enable mode. * Enable Mode - In order to enter the Enable mode (normal mode of operation), and to operate the outputs, the RST input must be high, and both Enable inputs EN1 and EN2 must also be high. 1 0x x0 1 11 * After entry to Enable Mode, the IC requires a pulse on Px_LS in order to charge the bootstrap capacitor before allowing the Px_HS to turn on. This pulse should be long enough to guarantee the bootstrap capacitor is charged (typically less than 50 s), but the IC does not enforce this condition. If there is an alternate means of pre-charging the bootstrap capacitor, i.e. an external resistor from Px_HS_S to GND, then a very brief pulse of 100 ns is sufficient to reset the logic. Table 6. Functional Ratings (TJ = -40C to 150C and supply voltage range VSUP = VPWR = 5.0 to 45 V, C = 0.47 F) Characteristic Default State of input pin Px_LS, EN1, EN2, RST, SI, SCLK, if left open (55) (Driver output is switched off, high-impedance mode) Default State of input pin Px_HS, CS if left open (55) (Driver output is switched off, high-impedance mode) Notes 55. To assure a defined status for all inputs, these pins are internally biased by pull-up/down current sources. High (>2.0 V) Value Low (<1.0 V) 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS LOGIC COMMANDS AND REGISTERS COMMAND DESCRIPTIONS The IC contains internal registers to control the various operating parameters, modes, and interrupt characteristics. These commands are sent and status is read via 8-bit SPI commands. The IC will use the last eight bits in an SPI transfer, so devices can be daisy-chained. The first three bits in an SPI word can be considered to be the Command with the trailing five bits being the data. The SPI logic will generate a framing error and ignore the SPI message if the number of received bits is not eight or if it is not a multiple of eight. After RST, the first SPI result returned is Status Register 0. Table 7. Command List Command 000x xxxx 0010 xxxx 0011 xxxx 010x xxxx 0110 xxxx Name NULL MASK0 MASK1 MODE CLINT0 Description These commands are used to read IC status. These commands do not change any internal IC status. Returns Status Register 0-3, depending on sub command. Sets a portion of the interrupt mask using lower four bits of command. A "1" bit enables interrupt generation for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0. Sets a portion of the interrupt mask using lower four bits of command. A "1" bit enables interrupt generation for that flag. INT remains asserted if uncleared faults are still present. Returns Status Register 0. Enables Desat/Phase Error Mode. Enables FULLON Mode. Locks further Mode changes. Returns Status Register 0. Clears a portion of the fault latch corresponding to MASK0 using lower four bits of command. A 1 bit clears the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0. Clears a portion of the fault latch corresponding to MASK1 using lower four bits of command. A 1 bit clears the interrupt latch for that flag. INT remains asserted if other unmasked faults are still present. Returns Status Register 0. Set deadtime with calibration technique. Returns Status Register 0. 0111 xxxx CLINT1 100x xxxx DEADTIME FAULT REPORTING AND INTERRUPT GENERATION Different fault conditions described in the previous chapters can generate an interrupt - INT pin output signal asserted high. When an interrupt occurs, the source can be read from Status Register 0, which is also the return word of most SPI messages. Faults are latched on occurrence, and the interrupt and faults are only cleared by sending the corresponding CLINTx command. A fault that still exists will continue to assert an interrupt. Note: If there are multiple pending interrupts, the INT line will not toggle when one of the faults is cleared. Interrupt processing circuitry on the host must be level sensitive to correctly detect multiple simultaneous interrupt. Thus, when an interrupt occurs, the host can query the IC by sending a NULL command; the return word contains flags indicating any faults not cleared since the CLINTx command was last written (rising edge of CS) and the beginning of the current SPI command (falling edge of CS). The NULL command causes no changes to the state of any of the fault or mask bits. The logic clearing the fault latches occurs only when: 1. A valid command had been received(i.e. no framing error); 2. A state change did not occur during the SPI message (if the bit is being returned as a 0 and a fault change occurs during the middle of the SPI message, the latch will remain set). The latch is cleared on the trailing (rising) edge of the CS pulse. Note, to prevent missing any faults the CLINTx command should not generally clear any faults without being observed; i.e. it should only clear faults returned in the prior NULL response. 33937 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS NULL COMMANDS This command is sent by sending binary 000x xxxx data. This can be used to read IC status in the SPI return word. Message 000x xx00 reads Status Register 0. Message 000x xx01 through 000x xx11 read additional internal registers. Table 8. NULL Commands SPI Data Bits Write Reset 7 0 6 0 5 0 4 x 3 x 2 x 1 0 0 0 NULL Commands are described in detail in the STATUS REGISTERS section of this document. MASK Command This is the mask for interrupts. A bit set to "1" enables the corresponding interrupt. Because of the number of MASK bits, this register is in two portions: 1. MASK0 2. MASK1 Both are accessed with 0010 xxxx and 0011 xxxx patterns respectively. Figure 20 illustrates how interrupts are enabled and faults cleared. CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively, but the action is to clear the interrupt latch and status register 0 bit corresponding to the lower nibble of the command. Table 9. MASK0 Register SPI Data Bits Write Reset 7 0 6 0 5 1 4 0 3 x 1 2 x 1 1 x 1 0 x 1 INTERRUPT HANDLING To Status Register From MASKx:N Register MASK Bit Various Faults From Clint Command INT Source INT Clear S Fault net N INT Latch R net 0 Figure 20. Interrupt Handling Table 10. MASK1 Register SPI Data Bits Write Reset 7 0 6 0 5 1 4 1 3 x 1 2 x 1 1 x 1 0 x 1 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Table 11. Setting Interrupt Masks Mask:bit MASK0:0 MASK0:1 MASK0:2 MASK0:3 MASK1:0 Description Over-temperature on any gate drive output generates an interrupt if this bit is set. Desaturation event on any output generates an interrupt if this bit is set. VLS under-voltage generates an interrupt if this bit is set. Over-current Error-if the over-current comparator threshold is exceeded, an interrupt is generated. Phase Error-if any Phase comparator output is not at the expected value when an output is command on, an interrupt is generated. This signal is the XOR of the phase comparator output with the output drive state, and blacked for the duration of the desaturation blanking interval. In FULLON mode, this signal is blanked and cannot generate an error. MASK1:1 MASK1:2 MASK1:3 Framing Error-if a framing error occurs, an interrupt is generated. Write Error after locking. Reset Event-If the IC is reset or disabled, an interrupt occurs. Since the IC will always start from a reset condition, this can be used to test the interrupt mechanism because when the IC comes out of RESET, an interrupt will immediately occur. MODE COMMAND This command is sent by sending binary 010x xxxx data. Table 12. MODE Command SPI Data Bits Write Reset 7 0 6 1 5 0 4 0 3 Desaturation Fault Mode 0 2 0 0 1 FULLON Mode 0 0 Mode Lock 0 * Bit 0-Mode Lock is used to enable or disable Mode Lock. If Bit 0 is set, changes to the internal registers are disallowed to prevent inadvertent changes. This bit cannot be cleared once set. Since the mode Lock mode can only be set, this bit prevents any subsequent, and likely erroneous, mode, deadtime, or mask register changes from being received. The only way to clear this bit is to RESET the IC. If an attempt is made to write to a register when Mode Lock is enabled, a Write Error fault is generated. * Bit 1-FULLON Mode. If this bit is set, programmed deadtime control is disabled, making it is possible to have both high and Low Side drivers in a phase on simultaneously. This could be useful in special applications such as alternator regulators, or switched-reluctance motor drive applications. There is no deadtime control in FULLON mode. Input signals directly control the output stages, synchronized with the internal clock. This bit is a "0", after RESET. Until overwritten, the IC operates normally; deadtime control and logic prevents both outputs from being turned on simultaneously. * Bit 3- Desaturation Fault Mode controls what happen when a desaturation event is detected. When set to "0", any desaturation on any channel causes all six output drivers to shutoff. The drivers can only be re-enabled by executing the CLINT command. When 1, desaturation faults are completely ignored. Bit 3 controls behavior if a Desaturation, or Phase Error event is detected. The possibilities are: -- 0: Default: When a Desaturation, or Phase Error event is detected on any channel, all channels turn off and generates an Interrupt, if interrupts are enabled. -- 1: Disable: Desaturation /Phase Error channel shutdown is disabled, but interrupts are still possible if unmasked. Sending a MODE command and setting the Mode Lock simultaneously are allowed. This sets the requested mode and locks out any further changes. 33937 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS DEADTIME COMMAND Deadtime prevents the turn-on of both transistors in the same phase until the deadtime has expired. The deadtime timer starts when a FET is commanded off (see Figure 6 and Figure 16). The deadtime control is disabled by enabling the FULLON mode. The deadtime is set by sending the DEADTIME command (100x xxx1), and then sending a calibration pulse of CS. This pulse must be 16 times longer than the required deadtime (see Figure 21). Deadtime is measured in cycle times of the internal time base, fTB. This measurement is divided by 16 and stored in an internal register to provide the reference for timing the deadtime between high and low gate transactions in the same phase. For example: the internal time base is running at 20 MHz and a 1.5 s deadtime is required. First a DEADTIME command is sent (using the SPI), then a CS is sent. The CS pulse is 16*1.5 = 24 s wide. The IC measures this pulse as 24000 ns/50 ns = 480 clock cycles and stores 480/16 = 30 in Table 13. .DEADTIME Command SPI Data Bits Write Reset 7 1 6 0 5 0 4 x the deadtime register. Until the next deadtime calibration is performed, 30 clock cycles will separate the turn off and turn on gate signals in the same phase. The worst case error immediately after calibration will be +0/-1 time base cycle, for this example +0 ns/-50 ns. Note that if the internal time base drifts, the effect on dead time will scale directly. Sending a ZERO DEADTIME command (100x xxx0) sets the deadtime timer to 0. However, simultaneous turn-on of High Side and Low Side FETs in the same phase is still prevented unless the FULLON command has been transmitted. There is no calibration pulse expected after receiving the ZERO DEADTIME command. After RESET, deadtime is set to the maximum value of 255 time base cycles (typically 15 s). The IC ignores any SPI data that is sent during the calibration pulse. If there are any transitions on SI or SCLK while the Deadtime CS pulse is low, a Framing Error will be generated, however, the CS pulse will be used to calibrate the deadtime 3 x x 2 x x 1 x x 0 ZERO/ CALIBRATE x CS CS Deadtime Calibration Pulse Deadtime Calibration Pulse SCLK SCLK SI SI Deadtime DEADTIME Command Command SO SO Figure 21. Deadtime Calibration 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS STATUS REGISTERS After any SPI command, the status of the IC is reported in the return value from the SPI port. There are four variants of the NULL command used to read various status in the IC. Other commands return a general status word in the Status Register 0. There are four Status Registers in the IC. Status Register 0 is most commonly used for general status. Registers one through three are used to read or confirm internal IC settings. Status Register 0 (Status Latch Bits) This register is read by sending the NULL0 command (000x xx00). It is also returned after any other command. This command returns the following data: Table 14. Status Register 0 SPI Data Bits Results Register 0 Read Reset 7 RESET Event 1 6 Write Error 5 Framing Error 0 4 Phase Error 3 Over-current 2 Low VLS 1 DESAT Detected on any Channel 0 0 TLIM Detected on any Channel 0 0 0 0 0 All status bits are latched. The latches are cleared only by sending a CLINT0 or CLINT1 command with the appropriate bits set. If the status is still present, that bit will not clear. CLINT0 and CLINT1 have the same format as MASK0 and MASK1 respectively. * Bit 0-is a flag for Over-temperature on any channel. This bit is the OR of the latched three internal TLIM detectors.This flag can generate an interrupt if the appropriate mask bit is set. * Bit 1-is a flag for Desaturation Detection on any channel. This bit is the OR of the latched three internal High Side desaturation detectors and phase error logic. Faults are also detected on the Low Side as phase errors. A phase error is generated if the output signal (at Px_HS_S) does not properly reflect the drive conditions. The phase error is the triple OR of phase errors from each phase. Each phase error is the OR of the HS and LS phase errors. An HS phase error (which will also trigger the desaturation detector) occurs when the HS FET is commanded on, and the Px_HS_S is still low in the deadtime duration after it is driven ON. Similarly, a LS phase error occurs when the LS FET is commanded on, and the Px_HS_S is still high in the deadtime duration after the FET is driven ON. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 2- is a flag for Low Supply Voltage. This bit is latched, thus a prior low voltage event is returned once before being cleared on read. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 3-is a flag for the output of the Over-current Comparator. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 4-is a flag for a Phase Error. If any Phase comparator output is not at the expected value when just one of the individual high or Low Side outputs is enabled, the fault flag is set. This signal is the XOR of the phase comparator output with the output driver state, and blanked for the duration of the desaturation blanking interval. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 5-is a flag for a Framing Error. A framing error is an SPI message not containing a multiple of eight bits (a 0-length message is also a framing error on 33937A). SCLK toggling while measuring the Deadtime calibration pulse is also a framing error. This would typically be a transient or permanent hardware error, perhaps due to noise on the SPI lines. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 6-indicates a Write Error After the Lock bit is set. A write error is any attempted write to the MASKn, Mode, or a Deadtime command after the Mode Lock bit is set. A write error is any attempt to write any other command than the one defined in the Table 7. This would typically be a software error. This flag can generate an interrupt if the appropriate mask bit is set. * Bit 7-is set upon exiting RST. It can be used to test the interrupt mechanism or to flag for a condition where the IC gets reset without the host being otherwise aware. This flag can generate an interrupt if the appropriate mask bit is set. 33937 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS Status Register 1 (MODE Bits) This register is read by sending the NULL1 command (000x xx01). This is guaranteed to not affect IC operation and returns the following data: Table 15. Status Register 1 SPI Data Bits Results Register 1 Read Reset 0 0 7 0 6 Desaturation Mode 5 Zero Deadtime Set 0 4 Calibration Overflow 3 Deadtime Calibration 2 0 1 FULLON Mode 0 Lock Bit 0 0 0 0 0 * Bit 0-Lock Bit indicates the IC registers (Deadtime, MASKn, CLINTn, and Mode) are locked. Any subsequent write to these registers is ignored and will set the Write Error flag. * Bit 1- is the present status of FULLON Mode. If this bit is set to "0", the FULLON mode is not allowed. A "1" indicates the IC can operate in FULLON Mode (both High Side and Low Side FETs of one phase can be simultaneously turned on). * Bit 3-indicates Deadtime Calibration occurred. It will be "0" until a successful Deadtime command is executed. This includes the Zero Deadtime setting, as well as a Calibration Overflow. * Bit 4-is a flag for a Deadtime Calibration Overflow. * Bit 5-is set if Zero Deadtime is commanded. * Bit 6-reflects the current state of the Desaturation/Phase Error turn-off mode. Status Register 2 (MASK bits) This register is read by sending the NULL2 command (000x xx10). This is guaranteed to not affect IC operation and returns the following data: Table 16. Status Register 2 SPI Data Bits Results Register 2 Read Reset 1 1 1 1 1 1 1 1 7 Mask1:3 6 Mask1:2 5 Mask1:1 4 Mask1:0 3 Mask0:3 2 Mask0:2 1 Mask0:1 0 Mask0:0 Status Register 3 (Deadtime) This register is read by sending the NULL3 command (000x xx11). This is guaranteed to not affect IC operation and returns the following data: Table 17. Status Register 3 SPI Data Bits Results Register 3 Read Reset 0 0 0 0 0 0 0 0 7 Dead7 6 Dead6 5 Dead5 4 Dead4 3 Dead3 2 Dead2 1 Dead1 0 Dead0 These bits represent the calibration applied to the internal oscillator to generate the requested deadtime. If calibration is not yet performed, all these bits return 0 even though the actual dead time is the maximum. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS IC Initialization Here is a possible flow to initialize the IC and its software environment. 1. Apply power (VSYS) to module 1.1. With RST still low, VSUP and VSYS current will be low because it will only be leakage and the small hold off bias current. 2. Remove RST (EN1 and EN2 are still low) 2.1. When RST rises above the threshold, the IC will power-up. The charge pump (if configured) will start, and VPWR and VLS will stabilize. 2.2. VDD will rise as the internal regulator charges the external reservoir capacitor and the IC will come out of reset. 2.3. Initialize interrupt handler for MCU 2.4. Interrupt will occur because of the RESET (Interrupt processing will occur here) 3. Initialize registers 3.1. Initialize MASK register by sending 0010 xxxx or 0011 xxxx to mask out unwanted interrupts. 3.2. Set desired dead time either by commanding zero dead time or calibrating the dead time. 3.3. Send MODE command with desired bits, and also the Lock bit. e.g. 01000001. This prevents further mode changes. 4. Bring EN1 & EN2 high 5. Initialize the outputs 5.1. Command all Px_LS and Px_HS to logic 1 simultaneously (command ON Low Side, sequentially switching the phases will reduce the transient with very large bootstrap capacitors and may prevent an unintended reset) 5.2. Command all Px_LS and Px_HS to logic 0 simultaneously (command ON High Side) 5.3. Command all Px_LS and Px_HS to logic 1 simultaneously (command ON Low Side) 5.4. The device is now ready for operation. MAIN LOOP 1. While (forever) 1.1. Send SPI messages (except NULL1-3), read results 1.2. If sending NULL1-3 messages, use a semaphore to detect interrupts 1.2.1. Set Semaphore flag in RAM 1.2.2. Send NULL1-3 1.2.3. Send NULL0, read SR1-3 1.2.4. If Semaphore is still set, then result is good, else go to 1.2.1 (because an interrupt has gotten in the way) 1.2.5. Clear semaphore 2. END Interrupt Handler When an interrupt occurs, the general procedure is to send NULL0 and NULL1 commands to determine what happened, take corrective action (if needed), clear the fault and return. Because the return value from an SPI command is actually returned in the subsequent message, main-loop software that tries to read SR1, SR2 or SR3, may experience an interrupt between sending the SPI command and the subsequent read. Thus if these registers are to be read, special care must be taken in the software to ensure that the correct results are being interpreted. 1. Interrupt Service Routine: 1.1. Disable further interrupts from the 33937 1.2. Clear semaphore set in 1.2.1 of Main loop. This indicates to the main loop that an interrupt occurred and that the return value it gets may not be as expected. 1.3. Send NULL0 Command. Ignore return value (the previous command is unknown) 1.4. Send NULL0 Command. The return value will be SR0 from the previous NULL0 command 2. Process Bits in SR0 and correct any faults 3. Send CLINT0 command to clear known (i.e. processed faults from SR0) faults 0:3 4. Send CLINT1 command to clear processed faults 4:7. Note, the return SR0 register from this command is actually read in the main routine. 5. Re-enable interrupts from the 33937 6. Return 33937 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSIS FEATURES PROTECTION AND DIAGNOSIS FEATURES Table 18. 33937 Fault Protection No. 1 Fault Phase Output Shorted to VSUP (High Side FET Shorted) Cause Wire harness shorted to battery * Detection Directly sensed by ADC as voltage across RSENSE Over-current Comparator output OC_OUT monitoring (Over-current Error) Low Side Phase Error Direct PHASEx output monitoring Desaturation Error High Side Phase Error Direct PHASEx output monitoring Directly sensed by the ADC as voltage across RSENSE Over-current Comparator output OC_OUT high (Over-current error) Desaturation Error High Side Phase Error Direct PHASEx output monitoring Desaturation Error High Side Phase Error Directly sensed by ADC as voltage across RSENSE Low Side Phase Error Directly sensed by ADC as voltage across RSENSE 33937 Protective Action Drain-to-Source short on the * High Side FET * * * * * * All external FETs turned off Fault bit set in Status Register INT pin set high OC_OUT pin set high 2 Phase Output Shorted to Ground (RSENSE Bypassed) Low Side FET Shorted Wire harness shorted to battery * * * * * * All external FETs turned off Fault bit set in Status Register INT pin set high 3 Drain-to-Source short on the * Low Side FET * * * * * * * * All external FETs turned off Fault bit set in Status Register INT pin set high OC_OUT pin set high 4 High Side FET Opened Low Side FET Opened Phase Output Opened (No Load) Module board assembly issue Module board assembly issue Wire harness open * * * * * * * * * * * All external FETs turned off Fault bit set in Status Register INT pin set high All external FETs turned off Fault bit set in Status Register INT pin set high 5 6 NOTE: Other protective actions should be taken at the system level by the controlling microcontroller or DSP. It is possible to disable all automatic shutdowns except for VLS undervoltage. Even when masked, faults will be registered by the status registers. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 39 TYPICAL APPLICATIONS PROTECTION AND DIAGNOSIS FEATURES TYPICAL APPLICATIONS VSYS +12V Nom. D1 C1 PUMP VPWR D2 C2 C6 To Other Two Phases VSUP VPUMP Main Charge Pump 5V Reg. VDD PGND Trickle Charge Pump VLS Reg. Hold -Off Circuit VLS Oscillator C3 VDD UV Detect C4 3x T-Lim Px_BOOT High -Side Driver Px_HS_G RST INT EN1 EN2 Px_HS Px_LS CS SI SCLK SO PHASE_x 3 3 3 VSUP Control Logic Desat. Comp. 1.4V Cx_Boot Rg_HS (Optional) QHS + - Phase x Output Px_HS_S QLS To Motor Phase VSUP Comp. Low -Side Driver Px_LS_G Rg_LS (Optional) Phase Return R1 OC_OUT GND Over-Cur. Comp. OC_TH + I-sense Amp. AMP_OUT AMP_N AMP_P VLS_CAP C5 Px_LS_S R3 + - R2 RSense To ADC Rfb Figure 22. Typical Application Diagram Using Charge Pump (+12 V Battery System) 33937 40 Analog Integrated Circuit Device Data Freescale Semiconductor TYPICAL APPLICATIONS PROTECTION AND DIAGNOSIS FEATURES VSYS +42V Nom. C6 +14V Nom. C2 To Other Two Phases PUMP VPWR VSUP VPUMP Main Charge Pump 5V Reg. VDD PGND Trickle Charge Pump VLS Reg. Hold -Off Circuit VLS Oscillator C3 VDD UV Detect C4 3x T-Lim Px_BOOT High -Side Driver Px_HS_G RST INT EN1 EN2 Px_HS Px_LS CS SI SCLK SO PHASE_x 3 3 3 VSUP Control Logic Desat. Comp. 1.4V Cx_Boot Rg_HS (Optional) QHS + - Phase x Output Px_HS_S QLS To Motor Phase VSUP Comp. Low -Side Driver Px_LS_G Rg_LS (Optional) Phase Return R1 OC_OUT GND Over-Cur. Comp. OC_TH + I-sense Amp. AMP_OUT AMP_N AMP_P VLS_CAP C5 Px_LS_S R3 + - R2 RSense To ADC Rfb Figure 23. High Voltage Application Diagram (+42 V Battery System) 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 41 TYPICAL APPLICATIONS PROTECTION AND DIAGNOSIS FEATURES 1 0.9 0.8 Power Dissipated (W) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 5 10 15 20 25 30 35 40 Supply Voltage (V) Figure 24. Power Dissipation Profile of Application Using Charge Pump Reference application with: * Pump capacitor: 1.0 F MLC * Pump filter capacitor: 47 F low ESR aluminum electrolytic * Pump diodes: MUR120 * Output FET gate charge: 240 nC @ 10 V * PWM Frequency: 20 kHz * Switching Single Phase Below approximately 17 V the charge pump is actively regulating VPWR. The increased power dissipation is due to the charge pump losses. Above this voltage the charge pump oscillator shuts down and VSYS is passed through the pump diodes directly to VPWR. 33937 42 Analog Integrated Circuit Device Data Freescale Semiconductor PROTECTION AND DIAGNOSIS FEATURES 1.500 1.400 1.300 1.200 1.100 Power Dissipation (W) 1.000 0.900 0.800 0.700 0.600 0.500 0.400 0.300 0.200 0.100 0.000 10 15 20 25 30 35 40 45 50 55 60 Supply Voltage (V) Figure 25. Power Dissipation Profile of Application Not Using Charge Pump Reference application with: * Output FET gate charge: 240 nC @ 10 V * PWM Frequency: 20 kHz * Switching Single Phase * No connections to PUMP or VPUMP * VPWR connected to VSYS If VPWR is supplied by a separate pre-regulator, the power dissipation profile will be nearly flat at the value of the pre-regulator voltage for all VSYS voltages. 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 43 PACKAGING PACKAGING DIMENSION PACKAGING PACKAGING DIMENSION For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below. EK SUFFIX (PB-FREE) 54-PIN 98ASA99334D ISSUE C 33937 44 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGING DIMENSION (CONTINUED) PACKAGING DIMENSION (CONTINUED) EK SUFFIX (PB-FREE) 54-PIN 98ASA99334D ISSUE C 33937 Analog Integrated Circuit Device Data Freescale Semiconductor 45 REVISION HISTORY REVISION HISTORY REVISION 1.0 2.0 DATE 6/2008 7/2008 DESCRIPTION OF CHANGES * * * * * * * * * * * * * * * * Initial Release Updated specifications for current sense amplifier and overcurrent comparator Added Gain/Phase curves for current sense amplifier Added typical curves for load margin on Px_CBOOT Added discussion about bootstrap capacitors and requirements for external bootstrap diodes Updated application drawings Added VSUP requirement for hold-off Updated Freescale form and style Added note to VLS Regulator Outputs (VLS, VLS_CAP)(2) Changed Charge Device Model - CDM Corrected title to No output loads on Gate Drive Pins, No PWM, Outputs initialized Changed CAUTION for 33937 only (Use the 33937A to avoid this CAUTION) and associated paragraphs Added PCZ33937AEK/R2 Part number throughout. Added Note and changed parameters for Desaturation Detector and Phase Comparator to Dynamic Electrical Characteristics Table. Replaced Typical Application Diagrams (Pages 40 and 41). Page 10 remove VDD Threshold (VDD Falling) change note 23 Note 41 clarification. 3.0 11/2008 4.0 12/2008 5.0 4/2009 * 33937 46 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2008-2009. All rights reserved. 33937 Rev. 5.0 4/2009 |
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